培训日期安排
This is the introduction of Assura training.
Assura Verification & Assura RCX

课程简介:
Assura系列产品是Cadence 新一代深亚微米模拟和混合IC版图验证、寄生参数提取以及分辩率增强可制造性解决方案。它采用层次化、多处理器模式等多种专利技术大大提高系统验证的精度和性能，还提供最佳的用户界面以快速定位和纠正错误，提高设计效率。Assura工具与Cadence 前端工具的原理图输入(Virtuoso Composer), 原理图输入(Virtuoso Composer), 模拟电路仿真环境(Analog Design Environment)以及后端的Virtuoso Layout Editor完美集成，使其形成全定制IC从前端到后端完整的设计流程。
 

课程目标:
*  Verify your physical IC design with Assura® Verification.
*  Set up and run DRC and LVS verification.
*  Locate and display results from DRC and LVS.
*  Run verification in various run and input modes.
*  Use Assura® Parasitic Extraction (RCX) to extract parasitic elemen
parasitic elements from your physical design.
*  Learn methods of simulating netlists with parasitic elements and performing analysis.
 

课程大纲:
 
Day 1
❏ Introduction
❏ Using Assura Verification
❏ Running design-rule checks (DRC)
Day 2
❏ Running layout versus schematic (LVS) checks
❏ Questions and answers
 
Day 3
❏ Introduction Parasitic primer
❏ RCX Overview
❏ Parasitic Simulation Setup and Analysis

培训日期：2008年9月9日-2008年9月11日(食宿自理)
名额限制：10人
地点：天大科技园A1座2楼
联系人：徐先生
电话：（+8622）66211352
传真：（+8622）66211339
E-mail：training@bicds.org