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Cadence工具培训通知(SoC)--培训日期:08-10-21至08-10-22
  • 来源:泰达科技创业网
  • 提交时间:2008-10-06 10:07:51
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  • 培训日期安排


    Title:SoC Encounter XL RTL-to-GDSII Hierarchical Flow
    Duration: 2 Days
    Version No.:7.1
    Overview
    Description

    In this course, you will explore high-level design planning, virtual prototyping, parasitic extraction, timing optimization and routing.

     

    You will use Tcl commands to prevent, analyze, and fix signal integrity problems. This course uses standard cells and custom blocks to illustrate SoC Encounter™ Global Physical Synthesis (GPS) features. You will use Tcl scripts to explore the design methodology.

     

    This course was formerly called SoC Encounter: Continuous Convergence (Flat & Hierarchical).


     
    In this course, you willRun timing optimization
    Run silicon virtual prototyping
    Run placement with the Amoeba placer
    Estimate parasitics and generate delay information
    Analyze congestion after running Trial Route
    Create clock trees
    Create physical partitions (hierarchy) and timing budgets
    Run signal integrity analysis
    Optimize timing
    Run NanoRoute™ Ultra detail routing
    Apply postroute timing and signal integrity optimization
    In this course, you will get a high-level technical overview of the SoC Encounter flow. However, to gain in-depth knowledge about each tool, refer to the Related Courses list and take the corresponding course(s).

     

    Audience
    ASIC Designers
    Design Engineers
    Chip Designers
    CAD Engineers
    CAD Developers
    Digital IC Designers

     

    Software
    SoC Encounter™ Global Physical Synthesis (GPS)
    Prerequisites

    This course is for designers with practical experience in Design methodology
    Place and route First Encounter™ GPS 

     

    Related Courses
    First Encounter XL
    NanoRoute Ultra


    Course Agenda

     

    Day1
    Overview
    Getting Started
    Selecting and Highlighting Objects in the Design
    Synthesizing the RTL
    Floorplanning the Design
    Planning Power
    Running Detail Placement
    Scan Optimization and Recordering
    Analyzing Route Feasibility with Trial Route

     

    Day2
    Extracting Parasitics and Analyzing Timing
    Optimizing and Closing Timing
    Implementing the Clock Tree
    Routing Power with Special Route
    Analyzing Power
    Partitioning the Design

     

    培训日期:2008年10月21日-2008年10月22日(食宿自理)
    名额限制:12人
    地点:天大科技园A1座2楼
    联系人:刘先生
    电话:(+8622)66211350
    传真:(+8622)66211339
    E-mail:liuzc@bicds.org

     

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